diff options
| author | Samuel Neves <[email protected]> | 2023-04-21 21:21:05 +0100 |
|---|---|---|
| committer | Samuel Neves <[email protected]> | 2023-04-21 21:28:01 +0100 |
| commit | 9ac0a9b896d71eb13ec697908307b8ad935eb145 (patch) | |
| tree | 36a2cc378fb8bb1c40ad66332cee52e74dcdb224 /c | |
| parent | a9750c7fec924db6a20fc87fa90269cdecbe75bd (diff) | |
correct SSSE3 detection; fixes #300
SSSE3 is indicated by bit 9 of ECX, not bit 0, which indicates the
presence of SSE3.
There are very few CPUs in use affected by this bug; SSE3 was part of
the Prescott new instructions, introduced in the later Pentium 4 chips,
whereas SSSE3 was introduced in Intel's Core 2 and AMD's Bulldozer. This
leaves a few Pentium 4 and Athlon 64 models that will potentially run an
illegal pshufb or pblendw.
Diffstat (limited to 'c')
| -rw-r--r-- | c/blake3_dispatch.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/c/blake3_dispatch.c b/c/blake3_dispatch.c index 0f348ef..2ab0093 100644 --- a/c/blake3_dispatch.c +++ b/c/blake3_dispatch.c @@ -101,7 +101,7 @@ static if (*edx & (1UL << 26)) features |= SSE2; #endif - if (*ecx & (1UL << 0)) + if (*ecx & (1UL << 9)) features |= SSSE3; if (*ecx & (1UL << 19)) features |= SSE41; |